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Semiconductor
HS-565ARH
Radiation Hardened High Speed, Monolithic Digital-to-Analog Converter
Description
The HS-565ARH is a fast, radiation hardened 12-bit current output, digital-to-analog converter. The monolithic chip includes a precision voltage reference, thin-film R-2R ladder, reference control amplifier and twelve high-speed bipolar current switches. The Harris Semiconductor Dielectric Isolation process provides latch-up free operation while minimizing stray capacitance and leakage currents, to produce an excellent combination of speed and accuracy. Also, ground currents are minimized to produce a low and constant current through the ground terminal, which reduces error due to code-dependent ground currents. HS-565ARH die are laser trimmed for a maximum integral nonlinearity error of 0.25 LSB at +25oC. In addition, the low noise buried zener reference is trimmed both for absolute value and minimum temperature coefficient.
March 1996
Features
* Devices QML Qualified in Accordance with MIL-PRF-38535 * Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96755 and Harris' QM Plan * DAC and Reference on a Single Chip * Pin Compatible with AD-565A and HI-565A * Very High Speed: Settles to 0.50 LSB in 500ns Max * Monotonicity Guaranteed Over Temperature * 0.50 LSB Max Nonlinearity Guaranteed Over Temperature * Low Gain Drift (Max., DAC Plus Reference) 50ppm/oC * Total Dose Hardness to 100K RAD * 0.75 LSB Accuracy Guaranteed Over Temperature (0.125 LSB Typical at +25oC)
Functional Diagram
REF OUT VCC 4 3 + BIP. OFF. 8 5K 10V IREF 0.5mA 3.5K 3K 7 -VEE 12 PWR GND + DAC IO (4X IREF X CODE) 2.5K 9.95K 5K 10 10V SPAN 9 OUT 11 20V SPAN
Applications
* High Speed A/D Converters * Precision Instrumentation * Signal Reconstruction
REF IN
6 19.95K
REF 5 GND
-
24 . . . 13 MSB LSB
Ordering Information
PART NUMBER
5962R9675501VJC 5962R9675501VXC HS1-565ARH (SAMPLE) HS9-565ARH (SAMPLE)
TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC +25oC +25oC
SCREENING LEVEL MIL-PRF-38535 Level V MIL-PRF-38535 Level V Sample Sample
PACKAGE 24 Lead SBDIP 24 Lead Ceramic Flatpack 24 Lead SBDIP 24 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) Harris Corporation 1996
Spec Number File Number
1
518795 3278.2
HS-565ARH Pinouts
HS1-565ARH MIL-STD-1835 CDIP2-T24 (SBDIP) TOP VIEW
NC 1 NC 2 VCC 3 REF OUT 4 REF GND 5 REF IN 6 -VEE 7 BIPOLAR RIN 8 IDAC OUT 9 24 BIT 1 IN (MSB) 23 BIT 2 IN 22 BIT 3 IN 21 BIT 4 IN 20 BIT 5 IN 19 BIT 6 IN 18 BIT 7 IN 17 BIT 8 IN 16 BIT 9 IN 15 BIT 10 IN 14 BIT 11 IN 13 BIT 12 IN (LSB)
10V SPAN 10 20V SPAN 11 PWR GND 12
H59-565ARH MIL-STD-1835 CDFP4-F24 (CERAMIC FLATPACK) TOP VIEW
NC NC VCC REF OUT REF GND REF IN -VEE BIPOLAR RIN IDAC OUT 10V SPAN 20V SPAN PWR GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 BIT 1 IN (MSB) BIT 2 IN BIT 3 IN BIT 4 IN BIT 5 IN BIT 6 IN BIT 7 IN BIT 8 IN BIT 9 IN BIT 10 IN BIT 11 IN BIT 12 IN (LSB)
Spec Number 2
518795
Specifications HS-565ARH
Absolute Maximum Ratings
VCC to Power Ground . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +18V VEE to Power Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to -18V Voltage on DAC Output (Pin 9) . . . . . . . . . . . . . . . . . . . . -3V to +12V Digital Input (Pins 13 - 24) to Power Ground . . . . . . . . . . -1V to +7V Ref In to Reference Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V Bipolar Offset to Reference Ground . . . . . . . . . . . . . . . . . . . . . . . 12V 10V Span R to Reference Ground. . . . . . . . . . . . . . . . . . . . . . . . . 12V 20V Span R to Reference Ground. . . . . . . . . . . . . . . . . . . . . . . . . 24V Junction Temperature (TJ) (Max) . . . . . . . . . . . . . . . . . . . . . +175oC Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC
Thermal Information
Thermal Resistance (Typical) JA (oC/W) JC (oC/W) SBDIP Package . . . . . . . . . . . . . . . . . . 60 17 Ceramic Flatpack Package 80 15 Maximum Package Power Dissipation at +125oC SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.83W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.62W If Device Power Exceeds Package Dissipation Capability, Provide Heat Sinking or Derate Linearly at the Following Rate: SBDIP Package 16.67mW/oC Ceramic Flatpack Package 12.5mW/oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range (VCC) . . . . . . . . . . . . . +11.4V to +16.5V Operating Voltage Range (VEE). . . . . . . . . . . . . . . -11.4V to -16.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Digital Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V Digital Input High Voltage . . . . . . . . . . . . . . . . . . . . . +2.2V to +5.5V
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUP 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE -55oC to +125oC -55oC to +125oC MIN TYP 0.125 MAX 12 0.75 UNITS Bits LSB
PARAMETERS Resolution Accuracy
SYMBOL
CONDITIONS VSSD = VSSA = 0V, VCC = +15V, VEE = -15V
ILE
VSSD = VSSA = 0V, VCC = +15V, VEE = -15V, Error Relative to Full Scale VSSD = VSSA = 0V, VIN = 5.5V VCC = +15V, VEE = -15V VSSD = VSSA = 0V, VIN = 0V VCC = +15V, VEE = -15V VSSD = VSSA = 0V, VCC = +15V, VEE = -15V, +25oC (Monotonicity Guaranteed Over Temp) VSSD = VSSA = 0V, VCC = +15V, VEE = -15V VSSD = VSSA = 0V, VCC = +15V, VEE = -15V VSSD = VSSA = 0V, VCC = +15V, VEE = -15V VSSD = VSSA = 0V, VCC = +15V, VEE = -15V, Available for external loads VSSD = VSSA = 0V, VCC = +15V, VEE = -15V, All Bits On VSSD = VSSA = 0V, VCC = +15V, VEE = -15V, All Bits On or Off
Digital Input High Current Digital Input Low Current Differential Nonlinearity
IIH IIL DLE
1, 2, 3 1, 2, 3 1, 2, 3
-55oC to +125oC -55oC to +125oC -55oC to +125oC
-20 -
0.01 -2.0 0.25
+1.0 0.50
A A LSB
Power Supply Currents VCC VEE Reference Output Voltage Reference Output Current Output Current Unipolar IOUT1 1, 2, 3 -55oC to +125oC -1.6 -2.0 -2.4 mA ICC IEE Ref Out IREF 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 -55oC to +125oC -55oC to +125oC -55oC to +125oC -55oC to +125oC -14.5 9.9 1.5 9.0 -9.5 10 2.5 11.8 10.1 mA mA V mA
Bipolar
IOUT2
1, 2, 3
-55oC to +125oC
0.8
1.0
1.2
mA
Spec Number 3
518795
Specifications HS-565ARH
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) GROUP A SUBGROUP 1, 2, 3 LIMITS TEMPERATURE -55oC to +125oC MIN TYP 0.01 MAX 0.05 UNITS % of F.S. % of F.S.
PARAMETERS Output Offset Unipolar
SYMBOL VOS
CONDITIONS VSSD = VSSA = 0V, VCC = +15V, VEE = -15V Figure 3, R2 = 50 Fixed VSSD = VSSA = 0V, VCC = +15V, VEE = -15V, R3 and R4 = 50 Fixed Figure 4
Bipolar
BPOE
1, 2, 3
-55oC to +125oC
-
0.05
0.15
Power Supply Gain Sensitivity VCC VEE Temperature Coefficients Unipolar Zero Bipolar Zero Gain (Full Scale) External Adjustments Gain Error Bipolar Zero Error NOTES: 1. All voltages referenced to VSSD = VSSA = 0V 2. Unless otherwise specified VCC = +15V and VEE = -15V. 3. The Power Supply Gain Sensitivity is tested in reference to a VCC = +15V and VEE = -15V. TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Table 2 Intentionally Left Blank. See AC Specifications in Table 3 TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETERS Output Capacitance Output Compliance Voltage Programmable Output Ranges SYMBOL COUT CONDITIONS f = 1MHz NOTES 1, 2 1 1 1 1 1 1 Gain Adjustment Range Bipolar Zero Adjustment Range Reference Input Impedance Output Resistance RREF ROUT Figures 3, 4 Figure 4 VSSD = VSSA = 0V, -15 VCC = +15V, VEE = -15V VSSD = VSSA = 0V, VCC = +15V, VEE = -15V, Exclusive of Span Resistors 1 1 1 1 -55 TEMPERATURE +25oC
oC
+PSS -PSS
Note 3 Note 3
1, 2, 3 1, 2, 3
-55oC to +125oC -55oC to +125oC
-
3 15
10 25
ppm of F.S./% ppm of F.S./%
With Internal Reference With Internal Reference With Internal Reference AE BPAE BPZE Fixed 50 Resistor for R2 Figures 3 Fixed 50 Resistor for R3 and R4, Figure 4 Fixed 50 Resistor for R3 and R4, Figure 4
1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
-55oC to +125oC -55oC -55oC -55oC to to to +125oC +125oC +125oC
-
1 5 10 0.10 0.10 0.05
2 20 50 0.25 0.25 0.10
ppm/oC ppm/oC ppm/oC % of F.S. % of F.S. % of F.S.
-55oC to +125oC -55oC to +125oC
MIN -1.5 0 -2.5 0 -5 -10 0.25 0.15 15K 1.8K
TYP 20 20K 2.5K
MAX 10 5 2.5 10 5 10 25K 3.2K
UNITS pF V V V V V V % of F.S. % of F.S.
to
+125oC
-55oC to +125oC -55 -55
oC
to to
+125oC +125oC
-55oC to +125oC
oC
-55oC to +125oC -55oC to +125oC -55oC to +125oC -55oC to +125oC -55oC to +125oC
Spec Number 4
518795
Specifications HS-565ARH
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETERS Settling Time (Note 3) SYMBOL TS1 CONDITIONS VSSD = VSSA = 0V, VCC = +15V, VEE = -15V, High Z External Load VSSD = VSSA = 0V, VCC = +15V, VEE = -15V, 75 External Load VSSD = VSSA = 0V, VCC = +15V, VEE = -15V VSSD = VSSA = 0V, VCC = +15V, VEE = -15V NOTES 1 TEMPERATURE -55oC to +125oC MIN TYP 350 MAX 500 UNITS ns
TS2
1
-55oC to +125oC
-
150
250
ns
Full Scale Transition Rise Time Fall Time NOTES: 1. The parameters listed in Table 3 are controlled via design or process and are not tested. These parameters are characterized upon initial design release. 2. 24 lead DIP package only. 3. Reference the Settling Time discussion and Figure 3. TABLE 4. POST 100 K RAD ELECTRICAL PERFORMANCE Post 100K RAD Electrical Performance Is Per Table 1 (+25oC Only) Except As Follows: LIMITS PARAMETER DIGITAL INPUTS Low Current Low Voltage High Voltage UNIPOLAR Full Scale Error BIPOLAR Offset Error Zero Error Full Scale Error Differential Nonlinearity Accuracy NOTES: 1. This parameter is an applied condition of test. TABLE 5. BI DELTA PARAMETERS (25oC) PARAMETER ICC IEE IOUT1 IOUT2 VOS AE BPOE BPZE IIL IIH DELTA LIMIT 1.18mA 1.45mA 240A 240A 0.02% 0.15% 0.10% 0.10% 1.0A 40nA BPOE BPZE BPAE DLE ILE Figure 4, R3 and R4 = 50 Fixed Figure 5, R3 and R4 = 50 Fixed Figure 5, R3 and R4 = 50 Fixed Monotonicity Guaranteed Error Relative to Full Scale 0.25 0.25 0.85 1.0 1.0 % of F.S % of F.S. % of F.S. LSB LSB AE Figure 3, R2 = 50 Fixed 0.85 % of F.S. IIL VIL VIH VIN = 0.0V (Note 1) (Note 1) -40 2.5 0.5 A V V SYMBOL CONDITIONS: +25 C ONLY
o
TRISE TFALL
1 1
-55oC to +125oC -55oC to +125oC
-
15 30
30 60
ns ns
MIN
MAX
UNITS
Spec Number 5
518795
Specifications HS-565ARH Burn-In Bias Circuit
1 NC +15V D1 C1 2 NC 3 VCC 4 REF OUT 5 REF GND -15V D2 C2 6 REF IN 7 -VEE 8 BIP OFF 9 OUT C3 BIT 1 24 BIT 2 23 BIT 3 22 BIT 4 21 BIT 5 20 BIT 6 19 BIT 7 18 BIT 8 17 BIT 9 16 F0 F1 +15V F2 F3 F4 F5 -15V F6 F7 F8 F9 F10 F11 +10V
Radiation Bias Circuit
1 NC 2 NC 3 VCC 4 REF OUT 5 REF GND 6 REF IN 7 -VEE 8 BIP OFF 9 OUT BIT 1 24 BIT 2 23 BIT 3 22 BIT 4 21 BIT 5 20 BIT 6 19 BIT 7 18 BIT 8 17 BIT 9 16 +5V
+10V D3
10 10V SPAN BIT 10 15 11 20V SPAN BIT 11 14 12 PWR GND BIT 12 13
10 10V SPAN BIT 10 15 11 20V SPAN BIT 11 14 12 PWR GND BIT 12 13
NOTES: D1 = D2 = D3 = IN4002 or Equivalent F0 to F11: VIH = 5.0V 0.5V VIL = 0.0V 0.5V F0 = 100kHz 10% (50% Duty Cycle) F1 = F0/2 F7 = F0/128 F2 = F0/4 F8 = F0/256 F3 = F0/8 F9 = F0/512 F4 = F0/16 F10 = F0/1024 F5 = F0/32 F11 = F0/2048 F6 = F0/64 NOTE: Power Supply Levels are 0.5V
Definitions of Specifications
Digital Inputs The HS-565ARH accepts digital input codes in binary format and may be user connected for any one of three binary codes. Straight binary, Two's Complement (see note below), or Offset Binary, (See Operating Instructions).
DIGITAL INPUT MSB . LSB 000 . . .000 100 . . .000 111 . . .111 011 . . .111 STRAIGHT BINARY Zero 0.50 FS +FS - 1LSB 0.50 FS - 1LSB ANALOG OUTPUT OFFSET BINARY -FS (Full Scale) Zero +FS - 1LSB Zero - 1LSB (NOTE) TWO'S COMPLEMENT Zero -FS Zero - 1LSB +FS - 1LSB
ideal (1 LSB) voltage change for a one bit change in code. A Differential Nonlinearity of 1 LSB or less guarantees monotonicity; i.e., the output always increases and never decreases for an increasing input. Settling Time Settling time is the time required for the output to settle to within the specified error band for any input code transition. It is usually specified for a full scale or major carry transition, settling to within 0.50 LSB of final value. Drift Gain Drift - The change in full scale analog output over the specified temperature range expressed in parts per million of full scale range per oC (ppm of FSR/oC). Gain error is measured with respect to +25oC at high (TH) and low (TL) temperatures. Gain drift is calculated for both high (TH - 25oC) and low ranges (+25oC - TL) by dividing the gain error by the respective change in temperature. The specification is the larger of the two representing worst case drift. Offset Drift - The change in analog output with all bits OFF over the specified temperature range expressed in parts per million of full scale range per oC (ppm of FSR/oC). Offset error is measured with respect to +25oC at high (TH) and low (TL) temperatures. Offset drift is calculated for both high (TH - 25oC) and low (+25oC - TL) ranges by dividing the offset error by the
NOTE: Invert MSB with external inverter to obtain Two's Complement Coding
Accuracy Nonlinearity - Nonlinearity of a D/A converter is an important measure of its accuracy. It describes the deviation from an ideal straight line transfer curve drawn between zero (all bits OFF) and full scale (all bits ON). Differential Nonlinearity - For a D/A converter, it is the difference between the actual output voltage change and the
Spec Number 6
518795
HS-565ARH
respective change in temperature. The specification given is the larger of the two, representing worst case drift. Power Supply Sensitivity Power Supply Sensitivity is a measure of the change in gain and offset of the D/A converter resulting from a change in -15V or +15V supplies. It is specified under DC conditions and expressed as parts per million of full scale range per percent of change in power supply (ppm of FSR/%). Compliance Compliance Voltage is the maximum output voltage range that can be tolerated and still maintain its specified accuracy. Compliance Limit implies functional operation only and makes no claims to accuracy. Glitch A glitch on the output of a D/A converter is a transient spike resulting from unequal internal ON-OFF switching times. Worst case glitches usually occur at half scale or the major carry code transition from 011 . . . 1 to 100 . . . 0 or vice versa. For example, if turn ON is greater than turn OFF for 011 . . . 1 to 100 . . . 0, an intermediate state of 000 . . . 0 exists, such that, the output momentarily glitches toward zero output. Matched switching times and fast switching will reduce glitches considerably. No Trim Operation The HS-565ARH will perform as specified without calibration adjustments. To operate without calibration, substitute 50 resistors for the 100 trimming potentiometers: In Figure 3 replace R2 with 50; also remove the network on pin 8 and connect 50 to ground. For bipolar operation in Figure 4, replace R3 and R4 with 50 resistors. With these changes, performance is guaranteed as shown under Specifications, "External Adjustments". Typical unipolar zero will be 0.50 LSB plus the op amp offset. The feedback capacitor C must be selected to minimize settling time.
R4 100 REF OUT VCC 4 3 R3 100 BIP. OFF. 8 11 HS-565ARH + 10V IREF 0.5mA 6 19.95K REF IN 5 REF GND 3.5K 3K CODE INPUT 7 -VEE PWR GND 24 . . . . . 13 MSB LSB + 9.95K DAC IO (4 x IREF x CODE) 2.5K 9 + R (SEE TABLE 7) 5K 5K 10 10V SPAN DAC OUT VO 20V SPAN
-
C
Applying the HS-565ARH
OP AMP Selection The HS-565ARH's current output may be converted to voltage using the standard connections shown in Figures 3 and 4. The choice of operational amplifier should be reviewed for each application, since a significant trade-off may be made between speed and accuracy. Remember settling time for the DAC-amplifier combination is
( t )2 + ( t )2 D A
FIGURE 4. BIPOLAR VOLTAGE OUTPUT
Calibration Calibration provides the maximum accuracy from a converter by adjusting its gain and offset errors to zero, For the HS-565ARH, these adjustments are similar whether the current output is used, or whether an external op amp is added to convert this current to a voltage. Refer to Table 7 for the voltage output case, along with Figure 3 or 4. Calibration is a two step process for each of the five output ranges shown in Table 7. First adjust the negative full scale (zero for unipolar ranges). This is an offset adjust which translates the output characteristic, i.e. affects each code by the same amount.
where tD, tA are settling times for the DAC and amplifier.
+15V 100k R2 100 REF OUT VCC 4 3 BIP. OFF. HS-565ARH + 19.95 K 3.5K 3K CODE INPUT 7 -VEE PWR GND 24 . . . . . 13 MSB LSB 10V IREF 0.5mA + 9.95K DAC IO (4 x IREF x CODE) 2.5K 9 + R (SEE TABLE 7) 5K 5K 10 10V SPAN DAC OUT VO 8 11 20V SPAN 100 R1 50k -15V
6 REF IN 5 REF GND
-
C
Next adjust positive FS. This is a gain error adjustment, which rotates the output characteristic about the negative FS value. For the bipolar ranges, this approach leaves an error at the zero code, whose maximum values is the same as for integral nonlinearity error. In general, only two values of output may be calibrated exactly; all others must tolerate some error. Choosing the extreme end points (plus and minus full scale) minimizes this distributed error for all other codes.
FIGURE 3. UNIPOLAR VOLTAGE OUTPUT
Spec Number 7
518795
HS-565ARH Settling Time
This is a challenging measurement, in which the result depends on the method chosen, the precision and quality of test equipment and the operating configuration of the DAC (test conditions). As a result, the different techniques in use by converter manufacturers can lead to consistently different results. An engineer should understand the advantage and limitations of a given test methods before using the specified settling time as a basis for design. The approach used for several years at Harris calls for a strobed comparator to sense final perturbations of the DAC output waveform. This gives the LSB a reasonable magnitude (814mV for the HS-565ARH, which provides the comparator with enough overdrive to establish an accurate 0.50 LSB window about the final settled value. Also, the required test conditions simulate the DACs environment for a common application - use in a successive approximation A/ D converter. Considerable experience has shown this to be a reliable and repeatable way to measure settling time. The usual specification is based on a 10V step, produced by simultaneously switching all bits from off-to-on (tON) or on-to-off (tOFF). The slower of the two cases is specified, as measured from 50% of the digital input transition to the final entry within a window of 0.50 LSB about the settled value. Four measurements characterize a given type of DAC: (a) tON, to final value +0.50 LSB (b) tON, to final value -0.50 LSB (c) tOFF, to final value +0.50 LSB (d) OFF, to final value -0.50 LSB (Cases (b) and (c) may be eliminated unless the overshoot exceeds 0.50 LSB). For example, refer to Figures 5A and5B for the measurement of case (d). Procedure As shown in Figure 5B, settling time equals tX plus the comparator delay (tD = 15ns). To measure tX, * Adjust the delay on generator number 2 for a tX of several microseconds. This assures that the DAC output has settled to its final wave. * Switch on the LSB (+5V) * Adjust the VLSB supply for 50% triggering at COMPARATOR OUT. This is indicated by traces of equal brightness on the oscilloscope display as shown in Figure 5B. Note DVM reading. * Switch to LSB to Pulse (P) * Readjust the VLSB supply for 50% triggering as before, and note DVM reading. One LSB equals one tenth the difference in the DVM readings noted above. * Adjust the VLSB supply to reduce the DVM reading by 5 LSBs (DVM reads 10X, so this sets the comparator to sense the final settled value minus 0.50 LSB). Comparator output disappears. * Reduce generator number 2 delay until comparator output reappears, and adjust for "equal brightness". * Measure tX from scope as shown in Figure 5B. Settling time equals tX + tD, i.e. tX + 15ns.
TABLE 7. OPERATING MODES AND CALIBRATION CIRCUIT CONNECTIONS MODE Unipolar (See Figure 3) OUTPUT RANGE 0 to +10V 0 to +5V Bipolar (See Figure 4) 10V 5V 2.5V PIN 10 TO VO VO NC VO VO PIN 11 TO Pin 10 Pin 9 VO Pin 10 Pin 9 RESISTOR (R) 1.43K 1.1K 1.69K 1.43K 1.1K APPLY INPUT CODE All 0's All 1's All 0's All 1's All 0's All 1's All 0's All 1's All 0's All 1's CALIBRATION ADJUST R1 R2 R1 R2 R3 R4 R3 R4 R3 R4 TO SET VO 0V +9.99756V 0V +4.99878V -10V +9.99512V -5V +4.99756V -2.5V +2.49878V
Spec Number 8
518795
HS-565ARH
OUT SYNC PULSE PULSE IN GENERATOR GENERATOR TRIG NO. 1 NO. 2 OUT 20V 20% BIAS HS-565ARH 24 23 . . . . . . . . . . . . . 14 13 8 11 5K 9.95K 10 NC 5K 9 B + 2.5K 2mA 12 5 STROBE IN D COMPARATOR OUT B A TURN ON TURN OFF OUT
C
A
+3V 50% 0V -0.50LSB 0V -400mV (TURN OFF) tX 2V
90 DVM 10 200K 0.1F VLSB SUPPLY D C
DIGITAL INPUT DAC OUTPUT SETTLING TIME tD = COMPARATOR DELAY COMP. STROBE "EQUAL BRIGHTNESS" COMP. OUT
~100 kHz
P 5V
LSB
50% 0.8V 4V 0V
FIGURE 5A.
FIGURE 5B.
Other Considerations
Grounds The HS-565ARH has two ground terminals, pin 5 (REF GND) and pin 12 (PWR GND). These should not be tied together near the package unless that point is also the system signal ground to which all returns are connected. (If such a point exists, then separate paths are required to pins 5 and 12). The current through pin 5 is near zero DC (Note); but pin 12 carries up to 1.75mA of code - dependent current from bits 1, 2, and 3. The general rule is to connect pin 5 directly to the system "quiet" point, usually called signal or analog ground. Connect pin 12 to the local digital or power ground. Then, of course, a single path must connect the analog/ signal and digital/power grounds.
NOTE: Current cancellation is a two step process within the HS565ARH in which code dependent variations are eliminated, the resulting DC current is supplied internally. First an auxiliary 9-bit R-2R ladder is driven by the complement of the DACs input code. Together, the main and auxiliary ladders draw a continuous 2.25mA from the internal ground node, regardless of input code. Part of the DC current is supplied by the zener voltage reference, and the remainder is sourced from the positive supply via a current mirror which is laser trimmed for zero current through the external terminal (pin 5).
Layout Connections to pin 9 (IOUT) on the HS-565ARH are most critical for high speed performance. Output capacitance of the DAC is only 20pF, so a small change of additional capacitance may alter the op amp's stability and affect settling time. Connections to pin 9 should be short and few. Component leads should be short on the side connecting to pin 9 (as for feedback capacitor C). See the Settling Time section. Bypass Capacitors Power supply bypass capacitors on the op amp will serve the HS-565ARH also. If no op amp is used, a 0.01F ceramic capacitor from each supply terminal to pin 12 is sufficient, since supply current variations are small.
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Die Size . . . . . . . . . . . . . . . . . . . . . . . . . 179 mils x 107 mils Tie Substrate to . . . . . . . . . . . . . . . . . . . .Reference Ground Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar - DI
Spec Number 9
518795
HS-565ARH Die Characteristics
DIE DIMENSIONS: 179 mils x 107 mils x 19 mils METALLIZATION: Type: Al/Copper Thickness: 16kA 2kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 2.0 x 105 A/cm2
Metallization Mask Layout
HS-565ARH
VCC 3 NC 3 NC 1 A (MSB) BIT 1 BIT 2
VREF OUT
BIT 3
VREF GND BIT 4 BIT 5
VREF IN -VS BIPOLAR 12 BIT 7 IDAC OUT BIT 8 BIT 6
BIT 9
10V SPAN 20V SPAN POWER GND BIT 12 (LSB) BIT 11 BIT 10
Spec Number 10
518795
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